| 摘要 |
A receiving/processing unit receives signals parallelized by a parallelizing unit, and executes a frame process including frame synchronization process on the signals. A phase comparing circuit and a phase judging circuit judge whether a bit delay is present based on a phase difference between a phase of a clock signal at a clock/data recovering unit and a phase of a clock signal at the parallelizing unit. The receiving/processing unit includes a logic processing circuit that executes a bit delay process based on a result of judgment by the phase comparing circuit and the phase judging circuit.
|
