| 摘要 |
<P>PROBLEM TO BE SOLVED: To disclose a method for performing a scan base test on a circuit using one or more test clock control structures, and a computer readable medium. <P>SOLUTION: This method includes a step of performing a test in a domain and implementing a first subset of a domain of a plurality of circuits provided with a dynamic defect detection test pattern. This method also includes a step of performing a test among the domains and implementing a second subset of the domain of the plurality of circuits provided with the dynamic defect detection test pattern. The dynamic defect detection test pattern can contain a last-shift-launch test pattern and a broad-side test pattern, for example. This method can include a step of constituting different programmable test clock controllers so that different clock domains may be tested mostly in parallel. <P>COPYRIGHT: (C)2008,JPO&INPIT |
