| 摘要 |
A semiconductor memory device is provided to reduce a leakage current of a data input circuit during test operation, and to prevent an operation error. A first data input circuit(100) receives a first data signal. A second data input circuit(200) transmits an internal data signal by receiving a second data signal, and is disabled in response to a test mode signal. An input control part(300) controls input timing of a data signal inputted to the first data input circuit and the second data input circuit. The first data input circuit comprises a NAND gate receiving the first data signal through one input port and receiving an input control signal provided from the input control part through the other input port.
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