发明名称 SYSTEM FOR VERIFYING TEST SIGNAL
摘要 PROBLEM TO BE SOLVED: To provide system for verifying test signal which can support accurate determination as to whether the measuring object meets standards, even when the bit error rate of the tested signal is low. SOLUTION: In this system, shift-amount setting section (33) calculates two shift amounts where bit error rate of transition bit at predefined threshold is to become the 1st error rate and their average value Dc, while the shift amount where the bit error rate at predefined threshold is to become the 2nd error rate is calculated, when the 2nd error rate of eye diagram display subject is different from the 1st one for transition bit; or the shift amount, in which the bit error rate at predefined threshold is to become the 2nd error rate for non-transition bit. In addition, threshold-setting section (34) calculates the threshold where the bit error rate is to become the 2nd error rate, when the shift amount is the average value Dc for displaying the eye diagram of the 2nd error rate for each presence of bit transition for reference pattern. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008014916(A) 申请公布日期 2008.01.24
申请号 JP20060189425 申请日期 2006.07.10
申请人 ANRITSU CORP 发明人 WADA TAKESHI;IMAZEKI HAJIME
分类号 G01R31/319;H04L25/02 主分类号 G01R31/319
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