发明名称 Selective plating of package terminals
摘要 In one embodiment, a method including providing a semiconductor pad package having a first pad and a second pad is disclosed. A first layer comprising a first metal is deposited on the first pad using a first process. A second metal is then deposited on the first pad and the first layer using a second process. In another embodiment, the first process comprises and electroplating process, and the second process comprises a direct immersion gold (DIG) process. In a further embodiment, the first pad is a power or ground pad, and the second pad is a signal pad.
申请公布号 US7321172(B2) 申请公布日期 2008.01.22
申请号 US20050227532 申请日期 2005.09.14
申请人 INTEL CORPORATION 发明人 WOOD DUSTIN P.;MALLIK DEBENDRA
分类号 H01L23/48;H01L21/48;H01L23/498;H05K3/24 主分类号 H01L23/48
代理机构 代理人
主权项
地址