发明名称 |
DRAM memory cell arrangement |
摘要 |
The present invention relates to a memory cell arrangement comprising a multiplicity of DRAM memory cells which are arranged in cell rows and cell columns and the selection transistor of which comprises in each case a first gate electrode and also a rear side electrode. The memory cell arrangement contains word lines and also rear side electrode lines which are arranged in each case alternately between adjacent cell columns. The invention provides for in each case the first gate electrodes of adjacent cell columns to be connected to the word line lying between the cell columns and in each case the rear side electrodes of adjacent cell columns to be connected to the rear side line lying between the cell columns. All the rear side lines are held at a constant potential, while for reading from a memory cell that word line is addressed to which the first gate electrode of the memory cell to be read is connected.
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申请公布号 |
US7321514(B2) |
申请公布日期 |
2008.01.22 |
申请号 |
US20050117853 |
申请日期 |
2005.04.29 |
申请人 |
INFINEON TECHNOLOGIES AG |
发明人 |
SCHWERIN ULRIKE GRUENING-VON |
分类号 |
G11C7/10;G11C5/00;G11C11/405;H01L21/8242;H01L27/02;H01L27/108 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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