发明名称 Method and apparatus for variable sigma-delta modulation
摘要 A method and apparatus for modulating a digital input signal is disclosed. The digital input signal is partitioned into a less-significant bit signal and a more-significant bit signal. A lower-order modulation of the less-significant bit signal is performed to generate an intermediate output signal. The intermediate output signal is appended to the more-significant bit signal to form an intermediate input signal. A higher-order modulation of the intermediate input signal is performed to generate a digital output signal. The higher-order modulation is of an order higher than the lower-order modulation. A phase-locked loop using the method and apparatus is disclosed.
申请公布号 US7321634(B2) 申请公布日期 2008.01.22
申请号 US20040015608 申请日期 2004.12.17
申请人 VERIGY (SINGAPORE) PTE. LTD. 发明人 KO HERBERT L.
分类号 H04L27/00 主分类号 H04L27/00
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