| 摘要 |
A memory circuit includes a latch having a first node and a second node, a first MIS transistor having source/drain nodes thereof coupled to the first node and to a plate line, respectively, and a gate node thereof coupled to a word selecting line, a second MIS transistor having source/drain nodes thereof coupled to the second node and to the plate line, respectively, and a gate node thereof coupled to the word selecting line, and a driver circuit configured to set the plate line to a first potential causing the first node to serve as a source node of the first MIS transistor in a first operation mode and to a second potential causing the first node to serve as a drain node of the first MIS transistor in a second operation mode, the first operation mode causing a lingering change in characteristics of the first MIS transistor.
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