| 摘要 |
Method and system for reducing bit error rate (BER) in a high-speed four-to-one time domain multiplexer are disclosed. In one embodiment of the present invention, a keep-alive current is employed in the latches of a four-to-one multiplexer in order to minimize the BER. By adjusting the keep-alive current of the latches in the datapath of the multiplexer, the latch performance can be optimized, thereby achieving minimum BER. Moreover, better latch performance can immunize the multiplexer against small timing misalignment.
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