发明名称 |
Bit stream conditioning circuit having adjustable PLL bandwidth |
摘要 |
A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface includes a line side interface, a board side interface, and a signal conditioning circuit. The signal conditioning circuit services each of an RX path and a TX path and includes a limiting amplifier and a clock and data recovery circuit. The signal conditioning circuit may also include an equalizer and/or an output pre-emphasis circuit. The clock and data recovery circuit has an adjustable Phase Locked Loop (PLL) bandwidth that is set to correspond to a jitter bandwidth of a serviced high-speed bit stream.
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申请公布号 |
US7321612(B2) |
申请公布日期 |
2008.01.22 |
申请号 |
US20030418035 |
申请日期 |
2003.04.17 |
申请人 |
BROADCOM CORPORATION |
发明人 |
TONIETTO DAVIDE;GHIASI ALI |
分类号 |
H04B1/38;G11B20/10;H04J3/04;H04J3/06;H04L1/20;H04L25/03;H04L25/20 |
主分类号 |
H04B1/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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