| 摘要 |
An apparatus a counter, storage units for storing count values interrupted by a row address whose refresh period is subject to change; comparator circuits for comparing the counter outputs and the contents of the storage units to each other as to whether or not the counter outputs coincide with the contents of the storage units; a holding circuit for setting an output hit signal to an active state when a coincidence signal is output from the comparator circuits and for resetting the hit signal to an inactive state in the next following clock cycle; a circuit performing control for not propagating a refresh clock signal to the counter when the hit signal is in an active state and for propagating the refresh clock signal to the counter when the hit signal is in an inactive state; a circuit for replacing an output of the counter by a row address which changes part of the counter output when the hit signal is in an activate state to replace the counter output with the row address whose refresh period is subject to change to output the row address whose refresh period is subject to change as a refresh address.
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