| 摘要 |
During testing frequency divider PS, test control voltage signal TC and RF test signal TS are supplied via balun Ti to input terminals IN 1 and IN 2. Test control voltage signal TC flows through resistors R 1, R 2 to turn on NPN transistor Q 0. A current from current source I 1 then ceases to be supplied through voltage-controlled oscillator V 1 and buffer B 10 to voltage-controlled oscillator V 1 and buffer B 10 to halt their operation. Output impedance of buffer B 10 is increased. Since potential of input terminals is that of test control voltage signal TC, varactor diodes VD 1, VD 2 are forward-biased, increasing capacitance values of the varactor diodes further. RF test signal TS may be supplied to frequency divider PS, through varactor diodes VD 1, VD 2, without being affected by buffer B 10 exhibiting high output impedance. Chip area of test circuit for PLL circuit is reduced.
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