发明名称 WAFER AND SEMICONDUCTOR DEVICE TESTING METHOD
摘要 A wafer and a semiconductor device testing method are provided to use a common probe card in spite of difference of models of a product, thereby reducing a cost. In a wafer, a plurality of chip regions(2) in each of which a semiconductor device is manufactured are partitioned by scribe lines(8). The wafer includes at least three pads(10A,10B,10C). The at least three pads are installed in the scribe line adjacent to the chip region and in contact with contact pins of a probe card. The three pads includes a power pad(10A), a grounding pad(10B), and a switching pad(10C). The power pad is connected to a power potential portion inside the chip region. The grounding pad is connected to a ground potential portion inside the chip region. The switching pad is connected to a semiconductor device inside the chip region and switches an operating state of the semiconductor device between a normal operating state and a standby state.
申请公布号 KR20080007134(A) 申请公布日期 2008.01.17
申请号 KR20070070171 申请日期 2007.07.12
申请人 SHARP KABUSHIKI KAISHA 发明人 FUJINO HIROAKI
分类号 H01L21/66 主分类号 H01L21/66
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