| 摘要 |
A semiconductor memory device is provided to improve operation characteristics of a bit line sense amplifier by reducing bit line capacitance by accessing each divided bit line pair selectively using a bit line separation control signal with a different level. A number of first bit line pairs and second bit line pairs are divided in a cell mat(400) including a number of memory cells. A first bit line separation control part(200) is controlled by a first bit line separation control signal, and connects a (2n)-th bit line pair of the first bit line pairs and a first bit line sense amplifier part(100) selectively. A second bit line separation control part(300) is controlled by a second bit line separation control signal, and connects a (2n+1)-th bit line pair of the first bit line pairs and the first bit line sense amplifier part selectively. A third bit line separation control part(500) is controlled by a third bit line separation control signal, and connects a (2n)-th bit line pair of the second bit line pairs and a second bit line sense amplifier part(700) selectively. A fourth bit line separation control part(600) is controlled by a fourth bit line separation control signal, and connects a (2n+1)-th bit line pair of the second bit line pairs and the second bit line sense amplifier part selectively.
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