| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To eliminate resampling of data wherein readout order deviates from writing order. <P>SOLUTION: Outputs of phase decision input circuits 28_2 and 30_2 having input outputs of phase decision registers 18_1 and 18_2 in synchronism with an exchanging clock are input to first and second memory read-on generating circuits 34_1 and 34_2 as the source signal generating means for memory read enable signals of first and second memories 26_1 and 26_2. The first and second memory read-on generating circuits determine from which of the first and second memories DDR data begins to be written based upon the signals supplied from the phase decision input circuits, and generate a source signal for a memory read enable signal to the memory where the data begins to be written first. <P>COPYRIGHT: (C)2008,JPO&INPIT</p> |
