| 摘要 |
PROBLEM TO BE SOLVED: To control a cache memory by a simple method. SOLUTION: The cache control circuit 3 comprises: an address versus data type table 4 for storing information of a correspondence relation between an address of a main memory 11 and a data type; a data type setting register 5 for setting information of a data type to be invalidated; a matching detector 6 for detecting whether the data type of data in a cache memory 2 is matched with a data type set in the data type setting register 5; and a line index counter 7 for generating a line index for accessing the cache memory 2 for every cache line. Since the address versus data type table 4, in which the information on the correspondence relation between the address range and the data type is stored, is provided, when a processor 1 designates a data type to be invalidated, cache lines corresponding to the data type can collectively be invalidated so that invalidation processing can easily and quickly be performed. COPYRIGHT: (C)2008,JPO&INPIT
|
