Random access memory including test circuit

摘要

A random access memory including input pads and a test circuit. The input pads are configured to receive a row address and a column address. The test circuit is configured to receive the row address and the column address via the input pads and to receive mask bits. The test circuit selects bits of the row address and the column address based on the mask bits and provides at least one test data bit based on the selected bits of the row address and the column address.