| 摘要 |
The present invention concerns a digital phase detector (PD) and also a method for digital phase detection, as can in particular be used e.g. in a so-called phase locked loop (PLL). According to the invention a digital phase detection signal (PD_OUT) is obtained, which specifies the phasing of an input clock signal (PD_IN) with reference to a higher frequency sampling clock signal (CK). In order hereby to overcome the limitation of the phase resolution as a result of a limited performance capability, in particular limited speed of the electronic components of a sampling device ( 14 ), a new kind of concept is used, in which the sampling clock signal (CK) is not immediately used for sampling ( 14 ), but is subjected beforehand to a digitally adjustable phase displacement ( 12 ). There originates an "auxiliary sampling clock signal" (CK< 1:8 >). The sampling ( 14 ) delivers a first, more significant digital component (OUT 1<9:0 >) of the phase detection signal (PD_OUT). Based on an evaluation of this first digital component (OUT 1<9:0 >) a phase displacement ( 12 ) is undertaken and a second digital component (OUT 2<12:0 >) of the phase detection signal (PD_OUT) is generated. The auxiliary sampling clock signal (CK< 1:8 >) is here adjustable in steps, which in each case are smaller than one period of the sampling clock signal (CK).
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