SETUP ERROR CORRECTING METHOD AND APPARATUS OF SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a setup error correction method and apparatus for reducing influence upon a layout by preventing excessive setup error correction. SOLUTION: An improvement factor estimation part 106 calculates the estimation of a delay value to be improved on the basis of a correction method determined by a correction method determining part 105 and progresses processing to an improvement factor determining part 107. The improvement factor determination part 107 calculates an improved predicted delay time from a delay time between the improvement factor estimated by the improvement factor estimation part 106 and a flip-flop. When the improved predicted delay time does not satisfy a requested delay time, an operation is returned to a correction place selection part 104 to continue correction processing of a setup error path. The correction processing of the setup error path is repeated until the improved predicted delay time satisfies the requested delay time or correction target places no longer exist. COPYRIGHT: (C)2008,JPO&INPIT