| 摘要 |
PROBLEM TO BE SOLVED: To provide a test clock circuit automatic insertion method capable of automatically inserting a test circuit capable of detecting a delay failure in an LSI after logic synthesis and reducing test facilitation design manhour. SOLUTION: A netlist 7 of LSIs after logic synthesis and before test facilitation design, STA (Static Timing Analysis) timing constraint information 8 and clock group information 9 are inputted (S1), a test clock circuit that can supply a test clock is inserted into a clock setting place by STA of an LSI after logic synthesis (S2), and a 0/1 control circuit that can externally control a logical value of a 0/1 case setting place which is set to a logic 0 or logic 1 in a system mode is inserted (S3) to perform test facilitation design circuit synthesis (S4). COPYRIGHT: (C)2008,JPO&INPIT
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