| 摘要 |
PROBLEM TO BE SOLVED: To provide a data processor compatible with a plurality of types of SIMD configurations and shortens the development period of a program. SOLUTION: At a decode stage in a low parallel execution mode, when the decode result is a high parallel instruction whose parallel degree is "4" (that is, 4 SIMD), a program control part 4A outputs an instruction code OP to indicate an NOP instruction in a cycle just after the high parallel instruction without incrementing a program counter PC. In indicating the high parallel instruction in a low parallel execution mode (that is, 2 SIMD), an arithmetic unit selection signal output part 23 divides the high parallel instruction into first and second partial parallel instructions which can be processed with a parallel degree "2", and outputs an arithmetic instruction selection signal OPS to indicate the first and second partial parallel instructions in two cycles starting from the next cycle to a parallel arithmetic unit 3. COPYRIGHT: (C)2008,JPO&INPIT
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