PROCESS FOR REMOVING HIGH STRESSED FILM USING LF OR HF BIAS POWER AND CAPACITIVELY COUPLED VHF SOURCE POWER WITH ENHANCED RESIDUE CAPTURE

摘要

A method of fabricating multilayer interconnect structures on a semiconductor wafer begins by roughening the interior surface of a metal lid to a surface roughness in excess of SA 2000 with a reentrant surface profile, and installing the metal lid as the ceiling of a plasma clean reactor chamber having a wafer pedestal facing the interior surface of the ceiling. Conductive vias are formed in a dielectric layer of the semiconductor wafer, which are then covered with an overlying dielectric layer. High aspect ratio openings are etched through the overlying dielectric layer to the conductive via to expose a face of the conductive via. This step is followed by a preclean step for removing residue from the exposed face of each conductive via while capturing at least a portion of the residue on the roughened interior surface of the lid. This preclean step consists of: (1) placing the wafer on the wafer pedestal of the plasma clean reactor chamber and introducing an inert gas into the preclean reactor chamber; (2) coupling VHF plasma source power of 60 MHz or greater to the wafer pedestal with sufficient power to establish an etch rate on the order of 200-500 Å/min; and (3) coupling LF or HF plasma bias power of 13.56 MHz or less with sufficient power to realize the etch rate at the bottom surfaces of the high aspect ratio openings, and removing the wafer from the plasma clean reactor chamber.