| 摘要 |
A lock-detection circuit that can set an acceptable phase-error range adapted to define a locked state and/or an unlocked state at a constant rate without being affected by a frequency and that can detect the locked state and/or the unlocked state with precision without being affected by various fluctuations and variations, and a PLL circuit including the lock-detection circuit. The range corresponding to a phase difference between first and second output signals is determined to be a locked-state range, where the phase of each of the first and second output signals delays or advances with reference to that of an oscillation-output signal transmitted from a voltage-controlled-oscillation circuit.
|
