| 摘要 |
A serial to parallel conversion circuit is provided. The circuit includes a shift register including flip-flops latch circuits, and control circuits. The flip-flops are connected in cascade, with a first stage flip-flop supplied with a transfer start signal that is sequentially transferred through the shift register, responsive to a shift clock signal. The latch circuits receive the output signals of the flip-flops, and latch and output a data signal, responsive to the output signals. The control circuits correspond to the flip-flops, and a first stage control circuit receives the shift clock signal and a start pulse and each remaining control circuit receives the shift clock signal and an output signal of a corresponding flip-flop. Each control circuit sets a state of a corresponding flip-flop to control a pulse width of an output signal. The frequency of said shift clock signal is set to lower than a data transfer frequency.
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