发明名称 BUS SYSTEM
摘要 It is so arranged that an appropriate deadline is assured with little consumption of power. A register ( 24 ) for remaining transfer time senses time that remains up to a limit by which data is to be transferred. A register ( 25 ) for remaining amount of data transfer senses the remaining amount of data that is to be transferred. The clock of the processing module is changed over dynamically based upon the remaining time sensed by the remaining transfer time register ( 24 ) and the remaining amount of transfer data sensed by the remaining transfer amount register ( 25 ).
申请公布号 US2008010391(A1) 申请公布日期 2008.01.10
申请号 US20070765172 申请日期 2007.06.19
申请人 CANON KABUSHIKI KAISHA 发明人 MORIYA KOJI
分类号 G06F13/36 主分类号 G06F13/36
代理机构 代理人
主权项
地址
您可能感兴趣的专利