发明名称 IEEE1394 COMMUNICATION APPARATUS
摘要 PROBLEM TO BE SOLVED: To provide a technology of reducing an overhead on a CPU due to start of unnecessary interrupt processing when using a communication LSI for generating an interrupt signal whose cycle is 125μs synchronously with an Isochronous cycle being a basic cycle in compliance with the IEEE1394. SOLUTION: The CPU in an IEEE1394 communication apparatus calculates an interrupt cycle required for transmission/reception of full packets at initialization on the basis of a communication cycle, number of connected communication apparatuses, a transmission/reception packet size, an Isochronous transmission/reception buffer size of the communication LSI, and a rate of reading/writing data from/to a buffer of the communication LSI by the CPU, frequency-divides the interrupt signal from the communication LSI and generates the interrupt signal with the interrupt cycle. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008005210(A) 申请公布日期 2008.01.10
申请号 JP20060172573 申请日期 2006.06.22
申请人 YASKAWA ELECTRIC CORP 发明人 MATSUO MASARU
分类号 H04L29/08 主分类号 H04L29/08
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