| 摘要 |
PROBLEM TO BE SOLVED: To resolve the problem that the power consumption is increased by occurrence of an instruction memory read at every cycle because of supply of one or more instructions in one cycle with respect to instructions issued from a CPU and is increased by the occurrence of simultaneous access of instruction memories at every cycle because of the increase in number of instruction memories for a multiprocessor configuration. SOLUTION: A means is provided which designates two-dimensional source registers and destination registers to an operand of an instruction, and an operation using a plurality of source registers is executed in a plurality of cycles to obtain a plurality of destinations. In an instruction to obtain destinations by using a plurality of source registers and consuming a plurality of cycles, a data rounding computing unit is connected to the last step of a pipeline. Furthermore, a plurality of CPUs are connected in series and use shared instruction memories in common. In this case, a field for controlling synchronization between adjacent CPUs is provided in an instruction operand of each CPU, whereby synchronization control is performed. COPYRIGHT: (C)2008,JPO&INPIT
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