| 摘要 |
PROBLEM TO BE SOLVED: To attain a microcomputer in which a CPU executes interruption processing without accessing a main memory in interrupting operation. SOLUTION: The microcomputer of the present invention has: a sub memory 13 accessed by the CPU 11 by way of an independent path; an address generation circuit 15 which generates the head address of an interruption vector table of the CPU 11 as a vector table address 14; a switching register 18 which holds control information indicating whether or not the vector table address 14 is included in an address space of the sub memory 13 and in which the control information is updated based on a switching signal 16 from the CPU 11 and an interruption control circuit 19 which determines the vector table address 14 generated by the address generation means 15 according to a control signal 17 output from the switching register 18 based on the control information and generates interruption to the CPU 11. COPYRIGHT: (C)2008,JPO&INPIT
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