发明名称 HIGH WITHSTAND VOLTAGE SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
摘要 PROBLEM TO BE SOLVED: To provide a high withstand voltage MOS semiconductor device capable of raising a withstand voltage in an off-state, and suppressing the deterioration of electric current ability. SOLUTION: A MOS transistor includes: a first conductivity-type well region 4 to be formed on a semiconductor layer 3; a second conductivity-type high concentration source region 6 to be selectively formed on the well region 4; a second conductivity-type high concentration drain region 5 which is formed on the semiconductor layer 3, so as to be separated from the well region 4; a second conductivity-type middle concentration deep well region 11 to be formed in a region including the drain region 5; a second conductivity-type low concentration drift region 10 which is formed from the end of the well region 4 to the side of the drain region 5 in the semiconductor layer 3, and does not reach an embedded insulating film 2; and a gate electrode 9 via a gate insulating film 8 between the end of the source region 6 and the end of the low concentration drift region 10. The surface concentration of the deep well region 11 is made to be not more than that of the low concentration drift region 10 in the MOS transistor. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008004783(A) 申请公布日期 2008.01.10
申请号 JP20060173309 申请日期 2006.06.23
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 TERASHITA TORU;SATO YOSHINOBU;OGURA HIROYOSHI;IKUTA AKIHISA
分类号 H01L21/336;H01L29/786 主分类号 H01L21/336
代理机构 代理人
主权项
地址