| 摘要 |
The invention relates to an arrangement (1) of a plurality of MOSFETs (Metal Oxide Semiconductor Field-Effect Transistor") on a chip having a first (10), a second (12) and a third connection (14), comprising at least a first MOSFET (Q1; Q2) serving as control cell (2) and at least a second MOSFET (Q3; Q4; Q5; Q6) serving as power cell (3), comprising a gate (G), source (S) and drain connection (D) respectively. According to the invention, the source connections (S) of all MOSFETs (Q1; Q2; Q3; Q4; Q5; Q6) are all connected to one another and in contact with the first connection (10) of the chip (5); the drain connection (D) of the at least one second MOSFET (Q3; Q4; Q5; Q6) serving as power cell (3) is in contact with the second connection (12) of the chip (5); the gate connections (G) of all MOSFETs (Q1; Q2; Q3; Q4; Q5; Q6) are all connected to one another and in contact with the third connection (14) of the chip (5); and gate (G) and drain (D) connections of the at least first MOSFET (Q1; Q2) serving as control cell are all connected to one another. |
