ARRAY SOURCE LINE IN NAND FLASH MEMORY

摘要

Methods (500,550) are disclosed for fabricating an array source line structure (112) in a wafer of a NAND flash memory device (100). One method aspect (500) comprises forming (510) a first oxide (610) and a nitride layer (611) of an ONO stack (620) over a substrate (604) and an STI (409 or 136) of the wafer (602 and 102), respectively, for example, then implanting (512) an N+ ion species through the stack (620) into a source line region (606) of the wafer (602). The method (500) further comprises forming (514) a second oxide layer (612) of the ONO stack (620) over the nitride layer (611) and forming an alumina layer (622) over the completed ONO stack (620) of the wafer (602), removing the ONOA stack (620,622) and forming (514) a gate oxide layer in the periphery region (not shown), then etching (516) an opening (626) in the ONOA stack (620) in an array source line region (606) of the wafer (602), for example, using a local interconnect mask. The method (500), also includes cleaning (518) the wafer and forming a polysilicon layer (628) over the wafer (602), and selectively etching (520) the polysilicon layer (628) and etching (522) the alumina layer (622) to concurrently form wordline (130) and select drain gate structures (124) in bitline contact regions (605, 608), and select source gate (116) structures and array source line structures (634) in source line regions (606). Method (500) further includes implanting (522) an N-dopant ion species, for example, an MDD material in openings of source/drain regions (106) formed in the wafer (602). The method (500) also comprises forming (524) sidewall spacers in bitline contact regions (605) and source line contact regions (606), implanting (526) an array ion species in the bitline contact regions (605), and finally, forming a suicide layer (654) in the polysilicon layer (604) in a core region to form a conductive layer for gate (116, 124), bitline (110), wordline (130), the select gate (116), and the source line structure contacts (132). Thus, the method (500) permits concurrent formation of the word lines (130), select gates (116,124) and the array source lines (112) simultaneously to simplify and reduce the cost of the process, and to improve the yield without etching into the STI (409) or the use of a local interconnect structure.