| 发明名称 |
Method and apparatus for performing incremental placement for layout-driven optimizations on field programmable gate arrays |
| 摘要 |
A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes placing new logic elements (LEs) at preferred locations on a layout of an existing system. Illegalities in placement of the new LEs are resolved.
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| 申请公布号 |
US7318210(B1) |
申请公布日期 |
2008.01.08 |
| 申请号 |
US20060505038 |
申请日期 |
2006.08.16 |
| 申请人 |
ALTERA CORPORATION |
发明人 |
SINGH DESHANAND P.;BROWN STEPHEN D. |
| 分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
| 代理机构 |
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代理人 |
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