发明名称 |
Method of fabricating a CMOS device with dual metal gate electrodes |
摘要 |
A method of constructing a dual metal gate CMOS structure that uses an ultra thin aluminum nitride (AIN<SUB>x</SUB>) buffer layer between the metal gate and gate dielectric during processing for preventing the gate dielectric from being exposed in the metal etching process. After the unwanted gate metal is etched away, the CMOS structure is annealed. During the annealing, the buffer layer is completely consumed through reaction with the metal gate and a new metal alloy is formed, resulting in only a minimal increase in the equivalent oxide thickness. The buffer layer and gate metals play a key role in determining the work functions of the metal/dielectric interface, since the work functions of the original gate metals are modified as a result of the annealing process.
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申请公布号 |
US7316950(B2) |
申请公布日期 |
2008.01.08 |
申请号 |
US20040826665 |
申请日期 |
2004.04.16 |
申请人 |
NATIONAL UNIVERSITY OF SINGAPORE |
发明人 |
PARK CHANG SEO;CHO BYUNG JIN;BALASUBRAMANIAN NARAYANAN T. |
分类号 |
H01L21/8238;H01L21/28;H01L29/49;H01L29/51 |
主分类号 |
H01L21/8238 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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