发明名称 DDR II write data capture calibration
摘要 A calibration circuit for calibrating the input data path of a digital circuit is disclosed. A simple string of a repeating data pattern such as, e.g., "1100," is sent on the data path. The digital circuit captures the data using a clock signal, examines the data signal for the predetermined pattern and adjusts a delay applied to the data signal until the predetermined pattern is recognized. Then the delay is further adjusted until the predetermined pattern is no longer recognized indicating that an edge of the eye of the data is near a clocking edge of the clocking signal. The delay applied to the data signal is then further adjusted by a predetermined amount to position the clock edge near the center of the data eye.
申请公布号 US7318167(B2) 申请公布日期 2008.01.08
申请号 US20060640983 申请日期 2006.12.19
申请人 发明人
分类号 G06F1/04;G06F12/00 主分类号 G06F1/04
代理机构 代理人
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