| 摘要 |
A complete hardware design environment is available through a system level simulator. This hardware design environment provides a bit accurate simulator for carrying out hardware simulations in the system level simulator. These simulations take advantage of the computational capabilities of the simulation processor. To take advantage of the simulation processor's resources (e.g., certain FPU components), the signals used in the simulation are made to conform to the native word type of the simulation processor. The hardware blocks deployed in a design frequently use non-native (from the simulation processor's perspective) word types. The bit accurate simulator casts words (signals) defined in the hardware design from a non-native format to a multi-bit native format suitable for use by the simulation processor. At various stages in the simulation, the simulator checks the "value" of the signal to determine whether that value is allowed by a word format specified by the hardware design.
|
