| 摘要 |
A delay locked loop and a semiconductor memory device provided with the same are provided to improve the reliability of the semiconductor memory device by accurately generating a plurality of clock signals. A delay locked loop includes a first controller and a synchronizer(PL'). The first controller generates first up and down signals by comparing the phases of an input clock signal and one of even delay clock signals, generates a pulse signal by detecting one of rising and falling edges of the input signal, and varies a first control signal in response to the first up and down signals. The synchronizer includes a delay unit(14'). The delay unit consists of even delay cells of which each has a subordinate ring-type connection with one another, generates even delay clock signals having the same cycle with the input clock signal by varying a delay time of the delay cells in response to the first control signal, controls the transition of at least one of the delay clock signal, and completes the transition of the rest of the delay clock signal in response to the previous transition.
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