| 摘要 |
A column control circuit for controlling a data input/output section is provided to assure margin to reduce the width of an external clock in high speed and to assure stability in normal speed, by controlling pulse width of a column pulse according to the speed of a memory device. According to a column control circuit controlling input/output of memory cell data, a latch part(400) generates a column pulse by using a set signal and a reset signal. The column pulse is a column address selection signal. A set signal generation part(100) generates the set signal determining enable time of the column pulse by using an internal command input pulse generated from an external command. A reset part(300) generates the reset signal determining disable time of the column pulse by delaying the column pulse according to a signal of controlling operation speed of a memory device.
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