| 摘要 |
A shift register is provided to reduce the number of clock transmission lines by implementing start stages for outputting start pulses using a clock pulse and a source voltage. A shift register includes at least two clock transmission lines(222), plural stages(ST1-STn), and a start stage(201). The clock transmission lines transmit at least two clock pulses having different phases from one another. The stages receive the clock pulses from the transmission lines and output sequentially scan pulses. The start stage receives at least one clock pulses, generates start pulses, and enables the stages by supplying the generated start pulses to at least one of the stages.
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