| 摘要 |
A delay locked loop circuit is provided to output data correctly by preventing a synchronization inconsistency between output data and an internal clock. A delay locked loop circuit includes a first buffer(101), a first delay unit(102), a second delay unit(103), a phase detector(104), and a compensation unit(200). The first buffer receives and buffers an external clock, and outputs a reference clock. The first delay unit delays and outputs the reference clock as much as a first delay section. The second delay unit outputs a feedback clock by delaying a signal of the first delay unit as much as a second delay section. The phase detector compares the reference clock and a phase of the feedback clock, and outputs a phase control signal for controlling a delay operation of the first delay unit. The compensation unit detects a change of an external voltage, compensates and adjusts the second delay section of the second delay unit in response to a change quantity of the external voltage. |
