| 摘要 |
A delay locked loop circuit is provided to generate an internal voltage with proper timing by preventing delay error of a clock, by removing a microwave component included in a phase control signal outputted from a phase detection part of the delay locked loop circuit. A first buffer(101) outputs a reference clock by buffering an external clock. A first delay part(102) delays the reference clock by a first delay period. A second delay part(103) outputs a feedback clock by delaying a signal from the first delay part by a second delay period. A phase detection part(104) outputs a first phase control signal by comparing the phase of the reference clock with the phase of the feedback clock. A correction part(150) receives the first phase control signal, and generates a second phase control signal by removing a microwave component from the first phase control signal. A control part(105) controls delay operation of the first delay part in response to the second phase control signal from the correction part.
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