| 摘要 |
A synchronous semiconductor memory device and a driving method thereof are provided to prevent a write error during read-to-write operation according as adopting additive latency. A first shifting unit(318) shifts a read command signal as much as additive latency(AL) in response to an internal clock signal. A second shifting unit(320) shifts a write command signal as much as additive latency in response to the internal clock signal. A third shifting unit(324) shifts an output signal of the second shifting unit as much as CAS latency(CL). A write address control unit(322) generates a write address control signal in response to an output signal of the first shifting unit and the output signal of the second shifting unit.
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