DELAY LOCKED LOOP CIRCUIT

摘要

A delay locked loop circuit is provided to inhibit increase in locking time for delay period despite great differences of external voltage or temperature between before and after power down mode in a semiconductor memory device. A delay locked loop circuit includes a detecting unit(111) and a delay correcting unit(112). The detecting unit starts to operate in response to power down signal(p_down) enabled during power down mode. The detection unit detects the duration of power down mode to output the result of the duration at the power down mode. The delay correcting unit starts to operate in response to the result outputted by the detecting unit and corrects delay in accordance with the duration of the power down mode for generating internal clock(int_clk) in phase with external clock(CLK).