SCAN CHAIN CIRCUITRY THAT ENABLES SCAN TESTING AT FUNCTIONAL CLOCK SPEED

摘要

Boundary scan circuitry that includes a plurality of scan cells that each contain two scan registers each for storing a respective test value. During on-chip or inter-chip testing, one of the scan registers is responsive to a functional clock signal so that the test cell generates transition delay test data having at least one state transition made at the speed of the functional clock signal. The transition delay test data allows the integrity of on-chip functional circuitry or the integrity of inter-chip circuitry to be verified at full functional speed.