发明名称 Singulation Process for Block-Molded Packages
摘要 Methods are disclosed for singulating block-molded IC packages. The methods of the invention include steps for making a partial cut in a block-molded semiconductor array, the partial cut defining the perimeter of an IC package and extending partially through the thickness of the array material. In a subsequent step, a final cut is made in alignment with the partial cut at the perimeter of the package such that the package is severed from adjacent material. Various embodiments of the invention are disclosed, including methods for making a plurality of partial cuts prior to making the final cut severing the package from the array, making cuts approaching from the same surface of the array, and making cuts approaching from opposing surfaces of the array. The partial cutting steps are used to prevent array warpage and facilitate hold-down during ball attach and/or singulation processes.
申请公布号 US2008003718(A1) 申请公布日期 2008.01.03
申请号 US20060428079 申请日期 2006.06.30
申请人 发明人 ESTEPA ERWIN REMOBLAS;ARGUELLES RONALDO MARASIGAN;BAUTISTA JESUS BAJO;PIAMONTE JOEY G.
分类号 H01L21/00 主分类号 H01L21/00
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