| 摘要 |
Disclosed is a duty cycle correction device for correcting a duty cycle of a clock signal output from a delay locked loop circuit. The duty cycle correction device includes a mixer for mixing phases of the first and second clock signals, thereby outputting a first signal, a phase splitter receiving the first signal and outputting a third clock signal, a duty detection unit receiving the third and fourth clock signals to detect a difference between duty cycles of the third and fourth clock signals, a combination unit for outputting a second signal, a shift register for outputting a first control signal, a phase detection unit receiving the first and second clock signals and outputting a second control signal representing a difference between duty cycles of the first and second clock signals. The mixer adjusts a mixing ratio by using the first and second control signals.
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