METHOD AND APPARATUS FOR BANDWIDTH EFFICIENT AND BOUNDED LATENCY PACKET BUFFERING

摘要

A system and method for buffering data packets in a data network device having a DRAM buffer are presented. When writing packets, the buffering system separates available memory channels into two groups corresponding to ingress and egress data. Based on the source of the data packets, data pages from the data packets are assigned to channels from either the ingress or egress group. Non-conflicting sets of addresses, called cachelines, are requested on each memory channel, and the data pages are evenly distributed over the assigned channels before being mapped to a cacheline. The number of read transactions currently being monitored by the system is controlled in order to reduce random packet read conflicts. Additionally, write and read transactions are grouped by an arbitration unit prior to being sent to the DRAM controller.