| 摘要 |
A method for manufacturing a semiconductor device is provided to prevent the misalignment of a gate and the short between a landing plug and the gate by maintaining step difference of a polysilicon layer formed at a scribe lane region. A semiconductor substrate(31) defined with a cell region(C) and a scribe lane region(S) is prepared. A recess gate groove(R) is formed at the cell region, and an alignment key(AR) is formed at the scribe lane region. A polysilicon layer(33) is deposited on the resultant structure. Halo ion-implantation is performed selectively in the polysilicon layer of the cell region, and ion-implantation is simultaneously performed in the polysilicon layer of the scribe lane region. Annealing is performed to the resultant structure including the ion-implanted polysilicon layer(33a). By performing CMP(Chemical Mechanical Polishing) the polysilicon layer of each region, the planarized polysilicon layer is formed in the cell region and an alignment key pattern is formed in the scribe lane region.
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