CAS LATENCY CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME

摘要

A CAS latency circuit and a semiconductor memory device having the same are provided to generate a stable CAS latency signal in a high speed semiconductor memory device, regardless of the variation of PVT(Process, Voltage, Temperature) or using an external clock with high frequency. An internal read command signal generation part(110) generates an internal read command signal(PREAD) in response to a read command. A latency clock signal generation part(120) generates a plurality of latency clock signals. A latency signal generation part(130) receives the internal read command signal and the latency control clocks, and generates a latency signal by shifting the internal read command signal. The latency control clock generation part generates at least one first latency control clock having a constant margin to the internal read command signal by using a PREAD replica.