| 摘要 |
A method for forming a self-aligned contact in a semiconductor memory device is provided to reduce an under-etch effect by increasing an etch rate of an interlayer dielectric. A gate(101) for drain or source selection transistor is formed on a semiconductor substrate(100). A spacer(103) is formed on a sidewall of the gate. An SAC nitride layer(104), and a first and second interlayer dielectrics(105,106) are formed on the entire structure including the spacer. An etch rate of the second interlayer dielectric is increased by implanting impurities into the inside of the second interlayer dielectric. A contact hole is formed by etching sequentially the second interlayer dielectric, the first interlayer dielectric, and the SAC nitride layer. A contact(109) is formed by burying the contact hole with a contact material.
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