| 摘要 |
A method for forming a wiring of a semiconductor device is provided to reduce a volume of a barrier metal layer and to increase a volume of a main wiring material by forming a lower part of the wiring with a damascene method and forming an upper part of the wiring with an RIE method. A first interlayer dielectric(23) is formed on a semiconductor substrate(20). An opening is formed by etching a predetermined region of the first interlayer dielectric. A first conductive layer(26) is formed by inserting a barrier metal layer(25) into the opening. A second conductive layer(27) is formed on the first conductive layer and the predetermined region of the first interlayer dielectric adjacent to the first conductive layer to form a wiring(28). A second interlayer dielectric is formed on the entire surface including the second conductive layer. The second interlayer dielectric is planarized to expose the second conductive layer.
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